Lim EJ, Kwong DL, Yeo YC (2009) Work function engineering within a single metal gate stack: manipulation terbium- and aluminium-induced interface dipoles of opposing polarity. Leung G, Pan A, Chui CO (2015) Junctionless silicon and In 0.53Ga 0.47As as transistors-Part II. In: Paul CK (ed) Advances in solid state circuits technologies. Huang AP, Yang CZ, Paul CK (2010) Hafnium-based high-k gate dielectrics. CSIJC 3(3):14–17Ĭlark RD (2014) Emerging applications for high K materials in VLSI technology. In: IEEE-ICSE proceedings, pp 232–235Ĭhakraborty R, Mandal JK (2017) Modelling of 5 nm gate length n-type MOSFET. An inverter is derived as an application of the CMOS from the MOSFET.Īfifah Maheran AH, Noor Faizah ZA, Menon PS, Ahmad I, Apte PR et al (2014) Statistical process modelling for 32 nm high-K/metal gate PMOS device. The proposed work optimizes the device dimensions by maintaining the electrical characteristics of CMOS. Voltage applied to the gate V GS, drain to source voltage V DS, threshold voltage V TH and drain current I D are the parameters taken to analysis electrical performance characteristics of the device in the present work and hence the results are validated with the simulation results. A CMOS device is also proposed using 4 nm MOSFETs. The performance of the proposed work is represented in terms of threshold voltage (V TH) of 0.3664 V, drive current (I ON) of 21.57 × 10 −6 A/μm, and leakage current (I OFF) of 20.12 × 10 −10 A/μm at drain voltage (V D) of 0.005 V. The gate length is downscaled to 4 nm with enhanced performance characteristics. Hafnium oxide (HfO 2) is used as oxide material and indium gallium arsenide (InGaAs) as semiconductor material. Using this MOSFET of gate length 4 nm a CMOS is designed and evaluated by its simulation results. By supplying a minimum drain voltage of 0.005 V a minimum I ON and I OFF current is achieved with a shorter channel length of 21.6 nm.

In this paper, the modelling and simulation of a 4 nm MOSFET device is proposed.

Mosfet what are some uses